According to the well-known “flip chip” integrated circuit mounting or packaging technique, an integrated circuit (IC) die is mounted in inverted fashion on a substrate, with solder bumps or other connection bumps on the face of the IC die bonded directly to solder connections on the substrate. It has been found that the useful life of the die/substrate assembly can be increased by providing a so-called “underfill” encapsulant to encapsulate the electrical connections between the die and the substrate. In most commercial flip chip manufacturing processes, a so-called “capillary” underfill is employed. With capillary underfill, the encapsulant is allowed to flow between the die and the substrate after the die bumps have been bonded to the substrate connections.
There are some concerns that the process step of applying capillary underfill may be excessively time-consuming, and so may become a bottleneck in the overall IC board or package manufacturing process. In an attempt to provide faster application of underfill, a so-called “no-flow” underfill process has been proposed in which underfill is applied to the substrate and/or to the die face before the die is bonded to the substrate. The no-flow underfill is displaced from the locus of the die/substrate electrical connections as a part of the bonding process.
One important characteristic of an underfill material is its coefficient of thermal expansion (CTE). Ideally the CTE of the underfill is close to the CTE of the electrical joint between the die and substrate. If the CTE of the underfill is substantially higher than that of the electrical joint, the joint may be stressed during thermal cycling and may experience joint fatigue, possibly leading to cracking and early failure.
Typical capillary underfill compositions are formed of a base (e.g., an epoxy system) having a relatively high CTE, filled with low-CTE filler particles (e.g. silica) to bring the overall CTE of the composition down to a desirable value. To achieve the desired low overall CTE, the degree of silica loading may be on the order of 60% to 65% by volume. However, such highly loaded materials have not proven to be satisfactory for use as no-flow underfills (i.e., for an underfill applied to a substrate or die before the die is bonded to the substrate), since, with a high degree of filler loading, filler particles may be trapped in the electrical joints, thereby possibly compromising the electrical connections between the die and substrate. This difficulty is not presented with capillary underfill, of course, since capillary underfill is applied after the electrical joint has been formed.
There accordingly is a problem as to how a no-flow underfill can be provided that has a suitably low CTE but will not interfere with joint formation between the IC die and the substrate. Interference with joint formation can be alleviated by reducing the degree of filler loading, but only with the disadvantage of higher underfill CTE, leading to possible reduction in useful life for the IC.